1. Field of the Invention
The present invention generally relates to structures for sense amplifier arrangement in semiconductor memory devices, and more particularly, it relates to structures for arranging sense amplifiers and bit line pairs in semiconductor memory devices.
2. Description of the Prior Art
FIG. 12 is a block diagram showing exemplary structure of a conventional dynamic random access memory (hereinafter referred to as "DRAM") which is well known in the art. Referring to FIG. 12, this DRAM includes a memory cell array 508 which comprises a matrix of a plurality of memory cells for storing data signals, an address buffer 504 which receives address signals for selecting the memory cells, a row decoder 505 and a column decoder 506 for decoding the address signals, and sense amplifier means 603 which is connected to the memory cell array 508 for amplifying and reading the signals stored in the memory cells. An input buffer 509 and an output buffer 600 for inputting and outputting the data signals respectively are connected to the memory cell array 508 through an I/O gate 507.
The address buffer 504 is connected to receive external address signals ext.A0 to ext.A9 or internal address signals Q0 to Q8 which are generated by a refresh counter 503. A refresh controller 502 drives the refresh counter 503 in response to timings of RAS and CAS signals supplied to a clock generator 501.
FIG. 13A is a circuit diagram showing peripheral circuits of the memory cell array 508 provided in the DRAM shown in FIG. 12. FIG. 13B is a timing chart for illustrating the operation thereof. These are disclosed in pp. 21 to 26 of a separate volume of "Electronics" March, issued by OHM-SHA on Mar. 5, 1986.
Referring to FIG. 13A, memory cells Mij are arranged and connected on intersection points between bit lines BLj and word lines WLi in a memory cell matrix 508a. Each memory cell Mij includes a capacitor Cs for storing a data signal and an N-channel MOS transistor Trs for switching. Each sense amplifier 603 includes a cross-coupling type sense amplifier which is connected between each pair of bit lines BLj and BLj. This sense amplifier 603 includes an N-channel sense amplifier which is formed by a pair of N-channel MOS transistors Tr1j and Tr2j. This N-channel sense amplifier is connected to the ground through an N-channel MOS transistor Tr3. The N-channel MOS transistor Tr3 has a gate which is connected to receive a sense trigger signal .phi.SE.
Read/write operation of the DRAM is now described with reference to FIGS. 13A and 13B.
The principle of operation of this DRAM is that, when no memory cell is accessed, .phi.P is at a high potential and both the bit lines BLj and BLj are equally held at high potentials (V.sub.CC), while each dummy cell 508b is maintained at the ground potential. After the potential of .phi.P is lowered, that at a word line WLi selected by the row address decoder 505 is increased so that data of the selected memory cell is read on the bit line BLj. In more concrete terms, the potential at the bit line BLj is unchanged if the data of the memory cell is a high potential, while electric charge flows from the bit line BLj into the memory cell so that the potential at the bit line BLj is slightly reduced when the data is a low potential. On the other hand, the potential at a dummy word line DW of the opposite bit line BLj is increased simultaneously with that at the word line WLi, so that data of the corresponding dummy cell 508b is read on the bit line BLj. In the dummy cell 508b, the ground potential is incorporated in a capacitor which is about half the memory cell size, and hence the potential at the bit line BLj is necessarily slightly reduced by an amount about half that in the case of reading a memory cell of a low potential.
Consequently, slight potential difference is caused between the bit lines BLj and BLj in this stage, such that the potential at the bit line BLj on the memory cell side is higher if the data of the memory cell is a high potential, while that of the bit line BLj on the dummy cell 508b side is higher if the data of the memory cell is a low potential. The potential difference between the bit lines BLj and BLj is small because parasitic capacitance is increased since a large number of memory cells are connected to one bit line. Then, the potential of .phi.SE is increased to drive the sense amplifier 603, thereby to enlarge the potential difference. The potential at the lower side bit line can be reduced to the ground level while maintaining the potential at the higher side bit line substantially unchanged. Further, an active pullup circuit 601 is driven to raise up the higher side bit line, the potential of which is slightly reduced, to a sufficiently high potential level. Thus, the high or low potential initially set in the memory cell is reproduced on the bit line which is connected to the memory cell.
Then, when the potential of a column select line CSLj selected by the column address decoder 506 is increased, the data of the selected memory cell can be read out since the bit line is connected with I/O and I/O lines, while data reproduced and amplified on the bit line can be again stored in the same memory cell when the potential of the word line is reduced in an unselected bit line. Data writing operation is performed in a simpler manner such that potentials at the word line and the column select line CSLj belonging to a memory cell selected by the row address decoder 505 and the column address decoder 506 are increased and the potential of writing data is applied to the bit lines BLj and BLj from the I/O and I/O lines, and thereafter the potential at the word line WLi is reduced to incorporate the data in the memory cell.
In the DRAM of the aforementioned structure, it has become increasingly difficult to match the arrangement space between the sense amplifiers with that between the memory cells which are connected in response to the sense amplifiers due to high densification of the memory cell array. The memory cell array of a conventional DRAM is generally provided in open bit line structure or folded bit line structure, depending on arrangement of bit line pairs which are connected to sense amplifiers.
FIG. 14 is a plan view conceptually showing the open bit line structure as an exemplary layout system of bit lines in a DRAM. Referring to FIG. 14, each sense amplifier SAj is connected with a pair of bit lines BLj and BLj, which are opposed to each other through the sense amplifier SAj. According to this open bit line structure, memory cells Mij are arranged one by one on intersection points between word lines WLi and the bit lines BLj and BLj. Thus, the open bit line structure is suitable for densification of the memory cells in view of layout efficiency. However, since each amplifier SAj is arranged in correspondence to each bit line, the arrangement space (pitch) between the sense amplifiers is influenced by the bit line space. It is impossible to relax the sense amplifier pitch since each sense amplifier is arranged within one memory cell pitch, and hence the open bit line structure is disadvantageous in view of design layout of the sense amplifiers.
FIG. 15 is a plan view conceptually showing the folded bit line structure as an exemplary layout system of bit lines in a DRAM. Referring to FIG. 15, each sense amplifier SAj is connected with a pair of bit lines BLj and BLj, which are arranged in parallel with each other. According to this folded bit line structure, two bit lines forming each bit line pair are close to each other to be substantially uninfluenced by dispersion caused in working, electrical noise or the like. Thus, this structure is advantageous in view of balance of the bit lines and sensitivity of the sense amplifiers as compared with the open bit line structure shown in FIG. 14. According to the folded bit line structure, further, each bit line pair formed by two adjacent bit lines is arranged in a memory cell array which is provided on one side of each sense amplifier, and hence the arrangement space (pitch) between the sense amplifiers can be relaxed from one memory cell pitch to two memory cell pitches. Thus, the folded bit line structure is relatively advantageous in design layout of the sense amplifiers as compared with the open bit line structure. According to this folded bit line structure, however, it is impossible to arrange memory cells Mij on all intersection points between word lines WLi and the bit lines BLj and BLj due to restriction in design layout. More specifically, memory cells are arranged at every other intersection of the word line and the bit line. Therefore, densification of the memory cell array, i.e., area reduction of the memory cell array region cannot be sufficiently attained.
There has been proposed a technique called pseudo folded bit line structure, as a bit line layout system which can reduce the area of the memory cell array region and relax the sense amplifier pitch. Such pseudo folded bit line structure is disclosed in U.S. Pat. No. 4,476,547 and Denshi Tsushin Gakkai Sogo Zenkoku Taikai Koen Ronbun-shu Bunsatsu 2, 1986, pp. 256-257, for example.
FIG. 16 is a plan view conceptually showing the pseudo folded bit line structure. According to this pseudo folded bit line structure, memory cells Mij are arranged on intersection points between pairs of bit lines BLj and BLj and word lines WLi, similarly to the open bit line structure. The memory cell array is divided into a plurality of subarrays along the word line direction, as shown by dotted lines in FIG. 16. In the example shown in FIG. 16, each subarray includes four memory cells in the word line direction. The memory cells included in each subarray deviate by half the memory cell pitch from those in the adjacent subarray. Similarly to the folded bit line structure, two bit lines are connected to one side of each sense amplifier to form a bit line pair. However, this structure is different from the folded bit line structure in the point that each bit line pair is formed by two bit lines which belong to different subarrays. Referring to FIG. 16, each subarray is formed by four bit lines. The bit lines BL1 to BL4 belonging to the upper subarray are connected to the sense amplifiers SA1 to SA4 respectively. The bit lines BL1 to BL4 belonging to the lower subarray are also connected to the sense amplifiers SA1 to SA4 respectively. Thus, each sense amplifier is connected with two bit lines, which belong to different subarrays. According to this structure, the sense amplifier pitch can be relaxed to two memory cell pitches similarly to the folded bit line structure, while the density of the memory cell array can be improved to a high level which is substantially equal to that of the open bit line structure.
However, in any bit line layout system of the generally proposed open bit line structure, folded bit line structure and pseudo folded bit line structure, arrangement of the sense amplifiers is restricted by the space between the bit lines, i.e., the memory cell pitch. Even if the folded bit line structure or the pseudo folded bit line structure is employed, the space between adjacent sense amplifiers cannot be relaxed in excess of two memory cell pitches. Therefore, it has been difficult to design a sense amplifier circuit responsive to desired characteristics of peripheral circuits which are connected to the sense amplifiers with no restriction by the layout of the memory cell array region. Further, the conventional sense amplifiers are arranged one by one in the longitudinal direction of the bit lines in response to the spaces between the bit lines forming the memory cell array, and hence it has been difficult to reduce the plane area of the region provided with the sense amplifier circuit.
FIG. 17 is a plan view conceptually showing arrangement of sense amplifiers in a prior art example disclosed in Japanese Patent Laying-Open No. 61-227292/(1986). According to this structure, a plurality of sense amplifiers are arranged in the longitudinal direction of bit lines. However, as the regions provided with the sense amplifiers are separated from the memory cell array region, spaces between the bit lines which are connected with the sense amplifiers are increased. Therefore, bit line pairs connected with different sense amplifiers cannot be identically spaced apart and hence it is impossible to form all bit line pairs by bit lines which are close to each other. Thus, the bit line structure shown in FIG. 17 is easily influenced by electrical noise etc. Further, interconnection regions required for forming the bit lines to be connected with the sense amplifiers are increased.